US 9,812,187 B2
Termination topology of memory system and associated memory module and control method
Shang-Pin Chen, Hsinchu County (TW); and Bo-Wei Hsieh, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsin-Chu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Feb. 5, 2017, as Appl. No. 15/424,882.
Application 15/424,882 is a continuation in part of application No. 15/390,692, filed on Dec. 26, 2016.
Claims priority of provisional application 62/363,379, filed on Jul. 18, 2016.
Claims priority of provisional application 62/362,079, filed on Jul. 14, 2016.
Claims priority of provisional application 62/298,005, filed on Feb. 22, 2016.
Claims priority of provisional application 62/298,005, filed on Feb. 22, 2016.
Prior Publication US 2017/0243629 A1, Aug. 24, 2017
Int. Cl. G11C 11/40 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 5/06 (2006.01); G11C 7/22 (2006.01)
CPC G11C 11/4076 (2013.01) [G11C 11/4093 (2013.01); G11C 5/06 (2013.01); G11C 7/22 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory controller, for selectively generating at least a clock signal and an inverted clock signal; and
a memory module, coupled to the memory controller, wherein the memory module receives at least the clock signal and the inverted clock signal from the memory controller, and the memory module comprises:
a first termination resistor, wherein a first node of the first termination resistor is to receive the clock signal;
a second termination resistor, wherein a first node of the second termination resistor is to receive the inverted clock signal; and
a switch module, couple between the first termination resistor and the second termination resistor, for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor.