| US 9,812,186 B2 | ||
| Reducing latency in an expanded memory system | ||
| Yuan Ruan, Beijing (CN); and Mingyu Chen, Beijing (CN) | ||
| Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN) | ||
| Filed by Huawei Technologies Co., Ltd., Shenzhen, Guangdong (CN) | ||
| Filed on Oct. 26, 2015, as Appl. No. 14/922,973. | ||
| Application 14/922,973 is a continuation of application No. PCT/CN2014/075068, filed on Apr. 10, 2014. | ||
| Claims priority of application No. 2013 1 0152306 (CN), filed on Apr. 27, 2013. | ||
| Prior Publication US 2016/0055898 A1, Feb. 25, 2016 | ||
| Int. Cl. G11C 11/406 (2006.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01) | ||
| CPC G11C 11/40607 (2013.01) [G06F 12/02 (2013.01); G06F 13/1673 (2013.01); G11C 7/1063 (2013.01); G11C 7/1072 (2013.01)] | 8 Claims |
| 4. A memory system, comprising:
a memory controller, a first level buffer chip, and at least one second level buffer chip, wherein the memory controller is
connected to the first level buffer chip and the at least one second level buffer chip, the first level buffer chip is cascaded
with the at least one second level buffer chip, the at least one second level buffer chip is connected to at least one memory
module, and the at least one memory module comprises at least one memory chip;
wherein the memory controller is configured to:
send a memory access instruction, a lower-order address signal, a first chip select signal, and a first higher-order address
signal to the first level buffer chip,
perform delay processing on a second higher-order address signal to obtain a delayed address signal,
send the delayed address signal to the at least one second level buffer chip, and
receive target data returned by the first level buffer chip, wherein the first chip select signal and the first higher-order
address signal are used to identify a target second level buffer chip in the at least one second level buffer chip, and the
lower-order address signal is used to identify a target memory chip in a target memory module;
wherein the first level buffer chip is configured to:
receive the memory access instruction, the lower-order address signal, the first chip select signal, and the first higher-order
address signal,
output a second chip select signal to the at least one second level buffer chip according to a preset mapping relationship,
the first chip select signal, and the first higher-order address signal to gate the target second level buffer chip,
send the memory access instruction and the lower-order address signal to the target second level buffer chip,
receive the target data returned by the target second level buffer chip, and
send the target data to the memory controller, wherein the at least one second level buffer chip comprises at least one buffer
chip, and the target second level buffer chip is a buffer chip that is gated by using the second chip select signal and is
in the at least one second level buffer chip; and
wherein the target second level buffer chip is configured to:
receive the memory access instruction, the lower-order address signal, the delayed address signal, and the second chip select
signal,
determine the target memory module from the at least one memory module according to the delayed address signal and the second
chip select signal,
determine the target memory chip from the target memory module according to the lower-order address signal,
acquire the target data from the target memory chip according to the memory access instruction, and
send the target data to the first level buffer chip, wherein the delayed address signal and the second chip select signal
are used to identify the target memory module in the at least one memory module.
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