US 9,812,185 B2
DRAM adjacent row disturb mitigation
David Edward Fisch, Pleasanton, CA (US); and William C. Plants, Campbell, CA (US)
Assigned to Invensas Corporation, San Jose, CA (US)
Filed by Invensas Corporation, San Jose, CA (US)
Filed on Feb. 9, 2016, as Appl. No. 15/19,788.
Claims priority of provisional application 62/244,494, filed on Oct. 21, 2015.
Prior Publication US 2017/0117030 A1, Apr. 27, 2017
Int. Cl. G11C 11/406 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/406 (2013.01) [G11C 11/4087 (2013.01)] 20 Claims
OG exemplary drawing
1. A method for mitigating data loss in a memory array with addressable rows, wherein each addressable row requires regular refresh operations, wherein each addressable row is physically adjacent to at least one other addressable row, and wherein the memory array is coupled (i) to a decoder further coupled to address inputs, and (ii) to command circuitry further coupled to command inputs, the method comprising:
(A) monitoring the command inputs to detect row activate commands;
(B) monitoring the address inputs to detect a sequence of active row addresses, each active row address associated with a row activate command;
(C) identifying one or more detected row addresses by presenting the sequence of active row addresses to a first filter coupled to the address inputs, the first filter detecting when an active row address occurs at a more frequent rate than a predetermined maximum rate; and
(D) presenting each detected row address to a second filter coupled to the first filter, wherein:
(i) upon a first detection of a detected row address that row address is stored in a tracked address memory location, each tracked address memory location being coupled to a first associated counter and a second associated counter, each counter having a stored value,
(ii) the first associated counter and the second associated counter are both reset when the detected row address is first stored in the tracked address memory location,
(iii) upon a subsequent detection of the detected row address in the tracked memory address location the first associated counter is incremented, and
(iv) upon detection of every detected row address the second associated counter is incremented, and
(v) wherein:
if the value in any first counter exceeds a first predetermined value,
then a non-regular data loss mitigation refresh operation is performed for the one or more addressable rows physically adjacent to detected row address stored in the associated tracked memory address location.