US 9,812,182 B2
Memory devices with improved refreshing operation
Yue-Der Chih, Hsinchu (TW); Cheng-Hsiung Kuo, Jhubei (TW); Gu-Huan Li, Zhubei (TW); and Chien-Yin Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Aug. 29, 2016, as Appl. No. 15/250,212.
Application 15/250,212 is a continuation of application No. 14/881,492, filed on Oct. 13, 2015, granted, now 9,455,006.
Application 14/881,492 is a continuation of application No. 14/067,907, filed on Oct. 30, 2013, granted, now 9,208,847, issued on Dec. 8, 2015.
Prior Publication US 2016/0372169 A1, Dec. 22, 2016
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 7/20 (2006.01); G11C 11/406 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); G11C 5/02 (2006.01)
CPC G11C 7/20 (2013.01) [G11C 5/02 (2013.01); G11C 11/1659 (2013.01); G11C 11/1677 (2013.01); G11C 11/406 (2013.01); G11C 13/0033 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0076 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first memory cell coupled to a bit line;
a second memory cell coupled to the bit line; and
a refresh module configured to read data in the second memory cell and then write the data back to the second memory cell in a condition that the first memory cell is programmed or erased.