US 9,812,181 B2
Memory circuit with transistors having different threshold voltages and method of operating the memory circuit
Chou-Ying Yang, Hsinchu (TW); Yi-Cheng Huang, Hsinchu (TW); and Shang-Hsuan Liu, Zhudong Town (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 21, 2015, as Appl. No. 14/601,652.
Application 14/601,652 is a continuation of application No. 13/681,030, filed on Nov. 19, 2012, granted, now 8,964,485.
Prior Publication US 2015/0138904 A1, May 21, 2015
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 7/12 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 7/06 (2013.01); G11C 7/1048 (2013.01); G11C 7/22 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a memory cell;
a data line configured to be coupled with the memory cell;
a node;
a precharge circuit configured to charge the node toward a predetermined voltage level;
a first transistor of a first type having a drain coupled with the node and a source coupled with the data line, the first transistor having a first threshold voltage;
a second transistor of the first type having a drain coupled with the node and a source coupled with the data line, the second transistor having a second threshold voltage different from the first threshold voltage;
a sense amplifier having a first input terminal and a second input terminal, the first input terminal of the sense amplifier being coupled with the node;
another memory cell;
another data line configured to be coupled with the another memory cell;
a third transistor of the first type having a drain coupled with the second input terminal of the sense amplifier and a source coupled with the another data line, the third transistor and the first transistor having substantially the same electrical characteristics; and
a fourth transistor of the first type having a drain coupled with the second input terminal of the sense amplifier and a source coupled with the another data line, the fourth transistor and the second transistor having substantially the same electrical characteristics.