US 9,812,180 B2
Programmable logic accelerator in system on chip
Hare Krishna Verma, Fremont, CA (US)
Filed by Hare Krishna Verma, Fremont, CA (US)
Filed on Jan. 18, 2016, as Appl. No. 14/997,595.
Prior Publication US 2017/0206939 A1, Jul. 20, 2017
Int. Cl. G11C 7/10 (2006.01); G11C 5/06 (2006.01)
CPC G11C 7/10 (2013.01) [G11C 5/06 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A programmable logic accelerator having a plurality of configuration memory blocks, each configuration memory block comprising:
a plurality of configuration memory banks, the plurality of configuration memory banks including a first configuration memory bank and a second configuration memory bank, the first configuration memory bank having one or more inputs and one or more outputs, the second configuration memory bank having one or more inputs and one or more outputs;
programmable control logic having one or more output and one or more inputs coupled to the first and second configuration memory banks, the one or more outputs from the programmable control logic capable of coupling to the one or more inputs of the first configuration memory bank, or capable of coupling to the one of more inputs of the second configuration memory banks, depending on a bank select signal; the programmable control logic including a configuration control logic and at least one multiplexer, the at least one multiplexer having inputs coupled to the configuration control logic and an output coupled to the first configuration memory bank or coupled to the second configuration memory bank, the configuration control logic generating the bank select signal to the at least one multiplexer;
wherein the programmable control logic programming the first configuration memory bank for configuring a programmable logic tile while the second configuration memory bank performing a first logic function, or programmable control logic programming the second configuration memory bank for configuring the programmable logic tile while the first configuration memory bank performing a second logic function, and wherein the overall performance of the programmable logic accelerator is not limited by configuration load penalty from the first and second configuration memory banks.