US 9,812,179 B2
Techniques for reducing disturbance in a semiconductor memory device
Jungtae Kwon, San Jose, CA (US); David Kim, Cupertino, CA (US); and Sunil Bhardwaj, San Jose, CA (US)
Assigned to OVONYX MEMORY TECHNOLOGY, LLC, Alexandria, VA (US)
Filed by OVONYX MEMORY TECHNOLOGY, LLC, Alexandria, VA (US)
Filed on Jun. 24, 2014, as Appl. No. 14/313,654.
Application 14/313,654 is a continuation of application No. 14/069,730, filed on Nov. 1, 2013, granted, now 8,760,906, issued on Jun. 24, 2014.
Application 14/069,730 is a continuation of application No. 13/465,982, filed on May 7, 2012, granted, now 8,699,289, issued on Apr. 15, 2014.
Application 13/465,982 is a continuation of application No. 12/624,856, filed on Nov. 24, 2009, granted, now 8,174,881, issued on May 8, 2012.
Prior Publication US 2014/0307512 A1, Oct. 16, 2014
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/406 (2006.01); G11C 7/02 (2006.01); G11C 7/06 (2006.01); G11C 7/18 (2006.01); G11C 11/4091 (2006.01); G11C 11/4097 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 7/08 (2006.01)
CPC G11C 7/02 (2013.01) [G11C 7/06 (2013.01); G11C 7/08 (2013.01); G11C 7/18 (2013.01); G11C 11/406 (2013.01); G11C 11/4091 (2013.01); G11C 11/4097 (2013.01); G11C 11/40618 (2013.01); G11C 16/32 (2013.01); G11C 16/3418 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of memory cells; and
data write and sense circuitry coupled to the plurality of memory cells, wherein the data write and sense circuitry comprises a plurality of local data sense amplifiers and a plurality of global data sense amplifiers, wherein the plurality of local data sense amplifiers are coupled to the plurality of memory cells via a plurality of local bit lines, wherein the plurality of global data sense amplifiers are coupled to the plurality of local data sense amplifiers via a plurality of global bit lines, wherein a first local data sense amplifier of the plurality of local data sense amplifiers is configured to determine a data state stored in a first memory cell of the plurality of memory cells during a first read operation, wherein a second local data sense amplifier of the plurality of local data sense amplifiers is configured to determine a data state stored in a second memory cell of the plurality of memory cells during a disturbance recovery operation after the first read operation, and wherein the disturbance recovery operation comprises a second read operation and a second writeback operation performed on the second memory cell before a first writeback operation is performed on the first memory cell.