US 9,812,177 B2
Circuit, method of using the circuit and memory macro including the circuit
Bing Wang, Palo Alto, CA (US); and Kuoyuan (Peter) Hsu, San Jose, CA (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 11, 2015, as Appl. No. 14/823,107.
Application 14/823,107 is a continuation of application No. 13/892,887, filed on May 13, 2013, granted, now 9,117,497.
Claims priority of provisional application 61/799,219, filed on Mar. 15, 2013.
Prior Publication US 2015/0348597 A1, Dec. 3, 2015
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01); G11C 8/08 (2006.01); G11C 8/12 (2006.01); G11C 8/16 (2006.01); G11C 11/418 (2006.01)
CPC G11C 5/063 (2013.01) [G11C 7/106 (2013.01); G11C 7/1012 (2013.01); G11C 7/18 (2013.01); G11C 8/08 (2013.01); G11C 8/12 (2013.01); G11C 8/16 (2013.01); G11C 11/418 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first latch configured to generate a first latched signal;
a first comparator configured to compare the first latched signal and a write row address of a second memory cell, and to generate a first comparator output signal;
a first logic circuit configured to receive the first comparator output signal and a fourth latched signal, and to generate a first logic circuit output signal;
a second latch configured to receive the first logic circuit output signal and to generate a second latched signal;
a third latch configured to generate a third latched signal;
a second comparator configured to compare the third latched signal and a read row address of a first memory cell, and to generate a second comparator output signal;
a second logic circuit configured to receive the second comparator output signal and the second latched signal, and to generate a second logic circuit output signal; and
a fourth latch configured to receive the second logic circuit output signal and to generate the fourth latched signal.