US 9,812,176 B2
Memory structure
Shih-Hung Chen, Hsinchu County (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Nov. 30, 2016, as Appl. No. 15/364,291.
Application 15/364,291 is a continuation of application No. 14/834,475, filed on Aug. 25, 2015, granted, now 9,542,979.
Prior Publication US 2017/0084310 A1, Mar. 23, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/02 (2006.01); G11C 16/10 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); H01L 23/528 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01)
CPC G11C 5/02 (2013.01) [G11C 5/025 (2013.01); G11C 5/06 (2013.01); G11C 7/10 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 16/10 (2013.01); H01L 23/528 (2013.01); H01L 27/11519 (2013.01); H01L 27/11565 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory structure, comprising:
N array regions, wherein N is an integer≧2, and each of the N array regions comprises:
a 3D array of a plurality of memory cells, wherein the memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array; and
a plurality of conductive lines disposed over and coupled to the 3D array, wherein the conductive lines have a pitch p, and p/d=⅕ to ½; and
N page buffers coupled to the N array regions, respectively;
wherein the N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines; and
wherein M array regions of the N array regions are configured to operate simultaneously, M is an integer, and M/N=1.