US 9,812,093 B2
Programmable power performance optimization for graphics cores
Linda L. Hurd, Cool, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 31, 2015, as Appl. No. 14/841,362.
Application 14/841,362 is a continuation of application No. 13/539,414, filed on Jun. 30, 2012, granted, now 9,122,632.
Prior Publication US 2015/0371610 A1, Dec. 24, 2015
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/14 (2006.01); G09G 5/36 (2006.01); G06F 1/32 (2006.01); G06F 9/38 (2006.01); G06F 12/0811 (2016.01); G06T 1/20 (2006.01)
CPC G09G 5/363 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3234 (2013.01); G06F 9/3836 (2013.01); G06F 12/0811 (2013.01); G06F 13/14 (2013.01); G06T 1/20 (2013.01); G06F 2212/283 (2013.01); G09G 2330/021 (2013.01); G09G 2330/025 (2013.01); G09G 2340/0435 (2013.01); G09G 2360/08 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
analysis logic to analyze a first frame of a scene, wherein the first frame is an initial frame of the scene or a subsequent frame of the scene;
determination logic to determine whether to perform one or more operations on one or more frames of the scene based at least in part on a second frame of the scene; and
execution logic to execute the one or more operations on a third frame of the scene based on a determination by the determination logic of whether to perform the one or more operations,
wherein one or more subsystems of a processor are to be power-gated based at least in part on a determination of which of the one or more operations are to be performed for each frame of the scene, wherein the determination logic is to determine which drawcalls, corresponding to the one or more operations, are to receive one or more types of modification based on a marker, wherein the one or more types of modification is to comprise one or more of: power-gating of the one or more subsystems or disabling of co-issue.