US 9,811,875 B2
Texture state cache
Benjiman L. Goodman, Cedar Park, TX (US); Adam T. Moerschell, San Jose, CA (US); and James S. Blomgren, Houston, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 10, 2014, as Appl. No. 14/482,828.
Prior Publication US 2016/0071232 A1, Mar. 10, 2016
Int. Cl. G09G 5/00 (2006.01); G06T 1/60 (2006.01); G06T 15/04 (2011.01)
CPC G06T 1/60 (2013.01) [G06T 15/04 (2013.01)] 18 Claims
OG exemplary drawing
1. An apparatus, comprising:
a texture state cache with multiple read ports that includes a plurality of entries configured to store state information relating to one or more textures stored by the apparatus, wherein the state information includes sampler state information that indicates how to process retrieved texel information to determine pixel attributes for texture samples; and
texture processing circuitry configured to retrieve state information for a particular one of the stored textures from one of the plurality of entries in the texture state cache and to determine pixel attributes based on the particular texture and retrieved state information;
wherein the texture processing circuitry includes a pipeline that includes multiple stages, including at least texture address generation, texture memory access, and texture filtering stages that are configured to access state information in the texture state cache in the same cycle using different respective ones of the multiple read ports.