US 9,811,690 B2
Protecting hidden content in integrated circuits
Jennifer L. Dworak, Dallas, TX (US); Alfred L. Crouch, Cedar Park, TX (US); Adam Zygmontowicz, Allen, TX (US); and John C. Potter, Austin, TX (US)
Assigned to Southern Methodist University, Dallas, TX (US)
Filed by Southern Methodist University, Dallas, TX (US)
Filed on Mar. 23, 2015, as Appl. No. 14/666,281.
Claims priority of provisional application 61/969,223, filed on Mar. 23, 2014.
Prior Publication US 2015/0349968 A1, Dec. 3, 2015
Int. Cl. G06F 21/00 (2013.01); G06F 21/79 (2013.01); G06F 21/72 (2013.01); G06F 21/80 (2013.01); G06F 21/75 (2013.01); G01R 31/3185 (2006.01); G06F 13/42 (2006.01)
CPC G06F 21/79 (2013.01) [G01R 31/318588 (2013.01); G06F 21/72 (2013.01); G06F 21/75 (2013.01); G06F 21/80 (2013.01); G06F 13/4282 (2013.01)] 77 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
one or more hidden content;
a first segment insertion bit circuit connected to at least one of the one or more hidden content;
a second segment insertion bit circuit connected to the first segment insertion bit circuit;
the first segment insertion bit circuit and the second segment insertion bit circuit form all or part of a serial data path;
the first segment insertion bit circuit provides access to the at least one of the one or more hidden content whenever the first segment insertion bit circuit is in a first specified state and prevents access to the at least one of the one or more hidden content whenever the first segment insertion bit scan cell circuit is in a different state than the first specified state;
the first segment insertion bit circuit does not interrupt the serial data path when the first segment insertion bit circuit in the first specified state or the different state;
whenever the second insertion bit circuit changes to a second specified state, the second segment insertion bit circuit changes an operational characteristic of the first segment insertion bit circuit by one or more of: (a) disabling the first segment insertion bit circuit, (b) causing a delay in changing the first segment insertion bit circuit to the first specified state, the different state, or both the first specified state and the different state, (c) causing the first segment insertion bit circuit or another circuit connected to the first segment insertion bit circuit or another circuit within the serial data path to operate at a slower scan shift frequency, (d) introducing a required change in a shift path voltage of the first segment insertion bit circuit or another circuit connected to the first segment insertion bit circuit or another circuit within the serial data path, or (e) automatically changing the first segment insertion bit circuit to the different state if the first segment insertion bit circuit is in the first specified state or preventing the first segment insertion bit circuit from being in the first specified state whenever one or more conditions are detected;
the second insertion bit circuit does not interrupt the serial data path when the second segment insertion bit is in any state; and
the first segment insertion bit circuit or the second segment insertion bit circuit requires clocking of a correct update value in an update cell and a correct key value in each of one or more key bits to change the segment insertion bit circuit to: (a) the first specified state, the different state, or both the first specified state and the different state with respect to the first segment insertion bit circuit, or (b) the second specified state, the different state, or both the second specified state and the different state with respect to the second segment insertion bit circuit.