US 9,811,627 B2
Method of component partitions on system on chip and device thereof
Yung-Chin Hou, Taipei (TW); Sandeep Kumar Goel, Dublin, CA (US); and Yun-Han Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Dec. 8, 2015, as Appl. No. 14/963,151.
Prior Publication US 2017/0161420 A1, Jun. 8, 2017
Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); G06F 17/50 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01)
CPC G06F 17/5072 (2013.01) [G06F 17/5077 (2013.01); H01L 21/486 (2013.01); H01L 21/76883 (2013.01); H01L 21/76898 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of partitioning a plurality of components of a system-on-chip (SOC), comprising:
sorting the plurality of components into a plurality of partitions according to a set of partition criteria; and
sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, wherein the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers.