US 9,811,626 B2
Method of designing layout of semiconductor device
Kwangok Jeong, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-do (KR)
Filed by Kwangok Jeong, Hwaseong-si (KR)
Filed on Sep. 9, 2015, as Appl. No. 14/848,758.
Claims priority of provisional application 62/052,076, filed on Sep. 18, 2014.
Claims priority of application No. 10-2015-0033280 (KR), filed on Mar. 10, 2015.
Prior Publication US 2016/0085897 A1, Mar. 24, 2016
Int. Cl. G06F 17/50 (2006.01)
CPC G06F 17/5072 (2013.01) 19 Claims
OG exemplary drawing
 
1. A method comprising:
receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning (SADP) process of a layout design system;
allocating an input and output area, a hard macro area, and a standard cell area at the target chip;
adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width, the unit placement width corresponding to a width between centers of adjacent gate lines to be formed in the standard cell area in the SADP process; and
forming a set of gate lines according to the SADP process in the standard cell area having adjusted-width cell rows, such that
adjacent gate lines of the set of gate lines are spaced apart from respective centers thereof by the unit placement width,
the set of gate lines extends across an entirety of the standard cell area, and
a quantity of gate lines, of the set of gate lines, in the standard cell area is an even number multiple gate lines.