US 9,811,625 B2
Computer-implemented method and computer program for generating a layout of a circuit block of an integrated circuit
James Edward Myers, Cambridge (GB)
Assigned to ARM Limited, Cambridge (GB)
Filed by ARM LIMITED, Cambridge (GB)
Filed on Apr. 28, 2015, as Appl. No. 14/697,709.
Prior Publication US 2016/0321389 A1, Nov. 3, 2016
Int. Cl. G06F 17/50 (2006.01); H01L 27/092 (2006.01); H01L 27/02 (2006.01)
CPC G06F 17/5072 (2013.01) [G06F 17/5077 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A computer-implemented method of generating a layout of a circuit block of an integrated circuit, comprising:
receiving input data identifying a plurality of circuit elements and interconnections required to implement the circuit block;
accessing a cell library providing a plurality of standard cells, each standard cell defining a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors;
forming a plurality of rows within which to place standard cells from the cell library in order to implement the circuit block, said plurality of rows including at least one body biased row in which a body bias is to be applied in respect of one type of the n-type transistors and the p-type transistors provided by the standard cells placed in that body biased row;
specifying constraint data identifying a subset of the standard cells that are allowed to be placed in each body biased row; and
generating said layout by placing standard cells within the plurality of rows having regard to the input data, an indication of each body biased row and the constraint data for each body biased row wherein the constraint data identifies as the subset of standard cells at least one standard cell that includes a series of transistors of the one type that are arranged in a stacked arrangement.