US 9,811,624 B2
Timing closure methodology including placement with initial delay values
Lukas P. P. P. van Ginneken, Clyde Hill, WA (US); and Prabhakar Kudva, New York, NY (US)
Assigned to Synopsys, Inc., Mountain View, CA (US); and International Business Machines Corporation, Armonk, NY (US)
Filed by Synopsys, Inc., Mountain View, CA (US); and International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 16, 2013, as Appl. No. 14/108,243.
Application 14/108,243 is a continuation of application No. 10/828,547, filed on Apr. 19, 2004, granted, now 8,621,403.
Application 10/828,547 is a continuation of application No. 10/134,076, filed on Apr. 24, 2002, granted, now 6,725,438, issued on Apr. 20, 2004.
Application 10/134,076 is a continuation of application No. 09/054,379, filed on Apr. 2, 1998, granted, now 6,453,446, issued on Sep. 17, 2002.
Claims priority of provisional application 60/068,827, filed on Dec. 24, 1997.
Prior Publication US 2014/0109034 A1, Apr. 17, 2014
Int. Cl. G06F 17/50 (2006.01)
CPC G06F 17/5072 (2013.01) [G06F 17/505 (2013.01); G06F 17/5068 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An electronic design automation tool executing, on a computer, an automated method for designing an electronic circuit to manufacture that is area-optimized, the method comprising:
configuring a host computer system comprising a microprocessor and a memory that stores an electronic circuit description and a cell library comprising a plurality of discrete electrical circuit component cells, the microprocessor configured to:
generate a netlist of a plurality of implementations of the electronic circuit description, each implementation comprising an arrangement of cells;
calculate, for each implementation of the electronic circuit description, a net weight describing a sensitivity of an area of the implementation to variations in load;
map an electronic circuit layout according to the implementation of the circuit associated with a lowest net weight, the map of the electronic circuit layout corresponding to the implementation having a lowest sensitivity for the electronic circuit; and
adjust a gate size of a cell of the mapped electronic circuit layout in a design to manufacture the electronic circuit, the gate size meeting one or more timing requirements associated with the electronic circuit.