US 9,811,502 B1
Architecture emulation in a parallel processing environment
Anant Agarwal, Weston, MA (US); and David M. Wentzlaff, Princeton Junction, NJ (US)
Assigned to Massachusetts Institute of Technology, Cambridge, MA (US)
Filed by Anant Agarwal, Weston, MA (US); and David M. Wentzlaff, Princeton Junction, NJ (US)
Filed on Aug. 19, 2013, as Appl. No. 13/969,718.
Application 12/128,073 is a division of application No. 11/414,421, filed on Apr. 28, 2006, granted, now 7,734,895.
Application 13/969,718 is a continuation of application No. 13/315,766, filed on Dec. 9, 2011, granted, now 8,516,222.
Application 13/315,766 is a continuation of application No. 12/128,073, filed on May 28, 2008, granted, now 8,078,832.
Claims priority of provisional application 60/675,612, filed on Apr. 28, 2005.
Int. Cl. G06F 15/76 (2006.01); G06F 9/455 (2006.01); G06F 9/30 (2006.01)
CPC G06F 15/76 (2013.01) [G06F 9/30174 (2013.01); G06F 9/455 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for emulating a guest instruction set architecture on an integrated circuit, the integrated circuit comprising a plurality of processor cores associated with a host instruction set architecture, the method comprising:
providing a spatial pipeline mapping to pass results of execution of a plurality of host processes that emulate guest functions performed in native instruction set architecture;
receiving by the plurality of processor cores guest instructions of the guest instruction set architecture, with each of the processor cores comprising a processor and a switch for interconnecting the processor cores;
running the plurality of host processes on a respective set of the plurality of processor cores, the host processes including instructions of the host instruction set architecture that emulate native hardware of the guest instruction set architecture; and
providing results of a first of the host processes to a second of the host processes according to the spatial pipeline mapping to execute the guest instructions.