US 9,811,498 B2
Implementing modal selection of bimodal coherent accelerator
Charles R. Johns, Austin, TX (US); Andrew T. Koch, Mountain View, CA (US); and Gregory M. Nordstrom, Pine Island, MN (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 27, 2015, as Appl. No. 14/696,929.
Application 14/696,929 is a continuation of application No. 14/606,296, filed on Jan. 27, 2015.
Prior Publication US 2016/0217101 A1, Jul. 28, 2016
Int. Cl. G06F 13/20 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); G06F 13/38 (2006.01); G06F 9/445 (2006.01); G06F 9/44 (2006.01)
CPC G06F 13/4282 (2013.01) [G06F 9/4411 (2013.01); G06F 9/44505 (2013.01); G06F 13/385 (2013.01); G06F 13/4022 (2013.01); G06F 13/4027 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method for implementing modal selection of a bimodal coherent accelerator in a computer system comprising: providing a system processor;
providing a Peripheral Component Interconnect Express (PCIE) standard Vendor Specific Extended Capability (VSEC) structure or Coherently Attached Processor Interface (CAPI) VSEC data in the configuration space of a CAPI-capable PCIE adapter;
providing configuration firmware in the computer system in which the PCIE adapter is installed
said system processor using the CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to detect, enable and control a coherent coprocessor adapter over PCIE;
said system processor enabling the CAPI-capable PCIE adapter to be bimodal and operate in a conventional PCI-Express (PCIE) transaction mode or a CAPI mode utilizing CAIA coherence and programming interface capabilities; and
wherein said CAPI-capable PCIE adapter is enabled to be selectively configured and enabled in either PCIE transaction mode or CAPI mode by configuration firmware in the computer system in which the PCIE adapter is installed.