US 9,811,495 B2
Arbitration signaling within a multimedia high definition link (MHL 3) device
Jiong Huang, Sunnyvale, CA (US); Lei Ming, San Jose, CA (US); Gyudong Kim, Sunnyvale, CA (US); and Young Il Kim, Sunnyvale, CA (US)
Assigned to Lattice Semiconductor Corporation, Portland, OR (US)
Filed by Silicon Image, Inc., Sunnyvale, CA (US)
Filed on Aug. 27, 2014, as Appl. No. 14/470,750.
Prior Publication US 2016/0062937 A1, Mar. 3, 2016
Int. Cl. H04B 1/44 (2006.01); G06F 13/40 (2006.01); G06F 13/362 (2006.01)
CPC G06F 13/4031 (2013.01) [G06F 13/362 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device for interfacing with a peer device via a multimedia communication link having a multimedia bus and a control bus in full duplex or in half duplex, the device comprising:
a half-duplex translation layer circuit to interface with software of the device in half duplex, the half-duplex translation layer circuit to exchange control data with the software and to communicatively couple to a half-duplex link layer circuit or a full duplex link layer circuit;
the full-duplex link layer circuit to communicate the control data with the peer device over the control bus in full duplex;
the half-duplex link layer circuit to communicate the control data with the peer device over the control bus in half duplex;
an arbitration circuit communicatively coupled between the half-duplex translation layer circuit and the full-duplex link layer circuit, the arbitration circuit to control data flow of the control data between the half-duplex translation layer circuit and the full-duplex link layer circuit by regulating transmission requests and receive requests; and
a multiplexing circuit communicatively coupled to the half-duplex translation layer circuit and configured to selectively connect the half-duplex link layer circuit or connect the full-duplex link layer circuit to the half-duplex translation layer circuit based on capabilities of the peer device.