US 9,811,493 B2
Semiconductor device
Masatsugu Kojima, Kamakura (JP); and Mitsuhiro Abe, Kawasaki (JP)
Assigned to TOSHIBA MEMORY CORPORATION, Minato-ku (JP)
Filed by TOSHIBA MEMORY CORPORATION, Minato-ku (JP)
Filed on Sep. 2, 2015, as Appl. No. 14/843,497.
Claims priority of provisional application 62/168,221, filed on May 29, 2015.
Prior Publication US 2016/0350253 A1, Dec. 1, 2016
Int. Cl. G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/4027 (2013.01) [G06F 13/4221 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory:
a data register coupled to the memory;
an input/output circuit coupled to the data register and configured to input and output data to and from an external controller which issues and transmits a command to the device,
wherein the input/output circuit includes:
a first clock generator configured to generate a first clock signal and transmit the first clock signal to a first signal line,
a first selector configured to receive first data from a first bus, receive second data from a second bus, and transmit one of the first and second data to a third bus,
a second selector configured to receive the one of the first and second data from the third bus, receive third data from a fourth bus, receive the first clock signal corresponding to the first and second data from the first signal line, receive a second clock signal corresponding to the third data from a second signal line, transmit one of the first to third data to a fifth bus, and transmit one of the first and second clock signals to a third signal line; and
a first-in-first-out (FIFO) circuit configured to receive the one of the first to third data from the fifth bus and receive the one of the first and second clock signals from the third signal line,
when a read operation of the one of the first and second data is executed, the FIFO circuit receives the one of the first and second data in response to the first clock signal within a period from when a read command and address data are received until a read enable signal is received from the external controller, and
when a read operation of the third data is executed, the FIFO circuit receives the third data in response to the second clock signal within the period.