US 9,811,468 B2
Set associative cache memory with heterogeneous replacement policy
Rodney E. Hooker, Austin, TX (US); Douglas R. Reed, Austin, TX (US); John Michael Greer, Austin, TX (US); and Colin Eddy, Austin, TX (US)
Assigned to VIA ALLIANCE SEMICONDUCTOR CO., LTD., Shanghai (CN)
Appl. No. 14/890,895
Filed by VIA ALLIANCE SEMICONDUCTOR CO., LTD., Shanghai (CN)
PCT Filed Dec. 14, 2014, PCT No. PCT/IB2014/003261
§ 371(c)(1), (2) Date Nov. 12, 2015,
PCT Pub. No. WO2016/097813, PCT Pub. Date Jun. 23, 2016.
Prior Publication US 2016/0357680 A1, Dec. 8, 2016
Int. Cl. G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/0864 (2016.01); G06F 12/128 (2016.01); G06F 12/127 (2016.01); G06F 9/45 (2006.01); G06F 12/0846 (2016.01)
CPC G06F 12/0864 (2013.01) [G06F 8/4442 (2013.01); G06F 12/127 (2013.01); G06F 12/128 (2013.01); G06F 12/0846 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/6032 (2013.04)] 15 Claims
OG exemplary drawing
 
1. A set associative cache memory, comprising:
an array of storage elements arranged as M sets by N ways;
an allocation unit that allocates the storage elements of the array in response to memory accesses that miss in the cache memory, wherein each of the memory accesses selects a set of the M sets;
for each parcel of a plurality of parcels, a parcel specifier that specifies:
a subset of ways of the N ways that are included in the parcel, wherein the subsets of ways of parcels associated with a selected set are mutually exclusive; and
a replacement scheme associated with the parcel from among a plurality of predetermined replacement schemes;
wherein for each memory access of the memory accesses, the allocation unit:
selects the parcel specifier of a parcel of the plurality of parcels in response to the memory access; and
uses the replacement scheme associated with the parcel to allocate into the subset of ways of the N ways of the selected set that are included in the parcel;
wherein each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs;
wherein the parcel specifier further associates one or more of the plurality of predetermined MATs with the parcel;
wherein the allocation unit selects the parcel specifier of a parcel of the plurality of parcels based on the MAT of the memory access; and
wherein the plurality of predetermined MATs includes at least three from the following list:
a memory access generated by a hardware prefetcher of the processor;
a memory access generated by a floating point instruction;
a memory access generated by a fused microinstruction;
a memory access generated by a media instruction;
a memory access generated by an instruction that modifies a memory address;
a memory access generated by a software prefetch instruction;
a memory access that loads an architectural descriptor;
a memory access generated by an instruction that specifies non-temporal data;
a memory access generated by an instruction that performs no alignment checks;
a memory access generated by a supervisor privilege level instruction;
a memory access generated by a zero extend instruction;
a memory access generated by a masked move instruction;
a memory access generated by a stack push instruction; and
a memory access generated by a hardware tablewalk engine of the processor.