US 9,811,466 B2
Expedited servicing of store operations in a data processing system
Guy L. Guthrie, Austin, TX (US); Hugh Shen, Round Rock, TX (US); Jeffrey A. Stuecheli, Austin, TX (US); and Derek E. Williams, Austin, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Aug. 28, 2015, as Appl. No. 14/839,310.
Prior Publication US 2017/0060746 A1, Mar. 2, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0842 (2016.01); G06F 12/0811 (2016.01); G06F 12/0831 (2016.01); G06F 12/0875 (2016.01)
CPC G06F 12/0842 (2013.01) [G06F 12/0811 (2013.01); G06F 12/0831 (2013.01); G06F 12/0875 (2013.01); G06F 2212/283 (2013.01); G06F 2212/452 (2013.01); G06F 2212/621 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A processing unit, comprising:
a processor core including:
an instruction sequencing circuit that orders instructions for execution; and
an execution circuit that generates a store operation by executing a store instruction in an instruction sequence;
a cache memory including a cache array and a store queue for buffering store operations to be serviced with respect to the cache array; and
a marking circuit within at least one of set including the processor core and the cache memory, wherein the marking circuit selectively marks the store operation as a high priority store operation, wherein the marking circuit marks the store operation as a high priority store operation in response to detecting, in the instruction sequence, a precursor instruction that precedes the store instruction in program order and that includes an opcode field indicating the store operation should be accorded high priority, and wherein the marking circuit refrains from marking the store operation as a high priority store operation in response to not detecting, in the instruction sequence, a precursor instruction that precedes the store instruction in program order and that includes an opcode field indicating the store operation should be accorded high priority;
wherein the cache memory expedites handling of the store operation in the store queue in response to the store operation being marked as a high priority store operation and otherwise refrains from expediting handling of the store operation in the store queue.