US 9,811,457 B2
Data placement based on data retention in a tiered storage device system
John Davis, Mountain View, CA (US); Ethan Miller, Mountain View, CA (US); Brian Gold, Mountain View, CA (US); John Colgrove, Mountain View, CA (US); Peter Vajgel, Mountain View, CA (US); John Hayes, Mountain View, CA (US); and Alex Ho, Mountain View, CA (US)
Assigned to Pure Storage, Inc., Mountain View, CA (US)
Filed by Pure Storage, Mountain View, CA (US)
Filed on Jan. 16, 2014, as Appl. No. 14/157,489.
Prior Publication US 2015/0199268 A1, Jul. 16, 2015
Int. Cl. G06F 12/02 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 2212/7202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor-based method for managing nonvolatile memory, comprising:
writing first data to a first type of flash memory, responsive to identifying that the first data is image data as a static property of the first data;
writing second data to a second type of flash memory having a lower error rate than the first type of flash memory, responsive to identifying that the second data is text data as a static property of the second data;
determining an error count or error rate during verification of the image or text data as a dynamic property of the image or text data; and
moving the image or text data to a differing location or differing type of flash memory, responsive to a value of the error count or the error rate representing the dynamic property exceeding a threshold, wherein the image data is associated with a first threshold error count or error rate that is independent of threshold error counts or error rates for other types of data written to the first type of flash memory, and the text data is associated with a second, differing threshold error count or error rate that is independent of threshold error counts or error rates for other types of data written to the second type of flash memory.