US 9,811,453 B1
Methods and apparatus for a scheduler for memory access
Srinivas Vaduvatha, Fremont, CA (US); Deepak Goel, San Jose, CA (US); and Shahriar Ilislamloo, Saratoga, CA (US)
Assigned to Juniper Networks, Inc., Sunnyvale, CA (US)
Filed by Juniper Networks, Inc., Sunnyvale, CA (US)
Filed on Jul. 31, 2013, as Appl. No. 13/955,733.
Int. Cl. G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 3/06 (2006.01)
CPC G06F 12/00 (2013.01) [G06F 3/0659 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory; and
a processing device operatively coupled to the memory, the processing device configured to be operatively coupled to each memory block from a plurality of memory blocks via a shared address bus,
the processing device configured to receive a first plurality of memory commands from a plurality of memory controllers, each memory controller of which is uniquely associated with a different memory block from the plurality of memory blocks,
the processing device configured to classify each memory command from the first plurality of memory commands into a category from a plurality of categories based at least in part on a second plurality of memory commands previously sent from the processing device to the plurality of memory blocks via the shared address bus, the plurality of categories including a category in which executions of a set of memory commands from the first plurality of memory commands are stalled,
causing a memory block from the plurality of memory blocks associated with the set of memory commands to be throttled,
the processing device configured to select an order in which to send each memory command from the first plurality of memory commands to the plurality of memory blocks via the shared address bus based at least in part on the category of each memory command from the first plurality of memory commands.