US 9,811,450 B2
Semiconductor test apparatus for controlling tester
Yukikazu Matsuo, Itami (JP); Yasuyuki Tanaka, Itami (JP); Masaru Sugimoto, Kawasaki (JP); and Kyosaku Nobunaga, Kodaira (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Kawasaki-shi, Kanagawa (JP)
Filed on Apr. 29, 2014, as Appl. No. 14/265,068.
Claims priority of application No. 2013-095289 (JP), filed on Apr. 30, 2013.
Prior Publication US 2014/0325191 A1, Oct. 30, 2014
Int. Cl. G06F 11/36 (2006.01); G06F 11/22 (2006.01)
CPC G06F 11/3688 (2013.01) [G06F 11/22 (2013.01); G06F 11/3656 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor test apparatus for controlling a tester to which a plurality of devices are connected, comprising:
a user program execution unit executing an instruction of a user program;
an instruction generation unit generating tester instructions for terminals of the plurality of devices connected to said tester based on the instruction of said user program;
an instruction storage unit storing generated said tester instructions;
a transfer mode setting unit setting a transfer mode to either a successive transfer mode or a batch transfer mode based on one of the instruction of said user program and information on how many tester instructions are stored in said instruction storage unit;
a transfer control unit transmitting the tester instructions in said instruction storage unit to said tester in accordance with set said transfer mode;
a memory storing a list of abnormal devices among the plurality of devices connected to said tester; and
a device management unit identifying an abnormal device among the plurality of devices connected to said tester in accordance with a signal transmitted from said tester and updating the list of said abnormal devices, wherein
said instruction generation unit generates the tester instructions as many as terminals of a normal device among the plurality of devices connected to said tester, by referring to the list of said abnormal devices based on the instruction of said user program,
said transfer mode setting unit sets the transfer mode to a mode shorter in transfer time period of the successive transfer mode and the batch transfer mode based on the information on how many tester instructions are stored in said instruction storage unit, and
the transfer time period of the successive transfer mode is (ts1+ts2)×N and the transfer time period of the successive transfer mode is tb1+tb2×N, in which ts1 represents a time period required for pre-processing for transfer in the successive transfer mode, ts2 represents a time period required for transfer of one tester instruction from said instruction storage unit to said tester in the successive transfer mode, tb1 represents a time period required for pre-processing for transfer in the batch transfer mode, tb2 represents a time period required for transfer of one tester instruction from said instruction storage unit to said tester in the batch transfer mode, and N represents the information on how many tester instructions are stored in said instruction storage unit.