US 9,811,429 B2
Microcontroller utilizing redundant address decoders and electronic control device using the same
Nobuyasu Kanekawa, Tokyo (JP); Hitoshi Arimitsu, Kanagawa (JP); Takashi Yasumasu, Kanagawa (JP); and Hideki Matsuyama, Kanagawa (JP)
Assigned to Renesas Electronics Corporation, Koutou-ku, Tokyo (JP)
Filed by Renesas Electronics Corporation, Kawasaki-shi, Kanagawa (JP)
Filed on May 6, 2015, as Appl. No. 14/705,127.
Claims priority of application No. 2014-105926 (JP), filed on May 22, 2014.
Prior Publication US 2015/0339201 A1, Nov. 26, 2015
Int. Cl. G06F 11/16 (2006.01); G06F 11/20 (2006.01); G06F 11/18 (2006.01)
CPC G06F 11/2053 (2013.01) [G06F 11/165 (2013.01); G06F 11/1616 (2013.01); G06F 11/1641 (2013.01); G06F 11/183 (2013.01); G06F 11/187 (2013.01); G06F 2201/85 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microcontroller comprising three or more processors and a storage device,
wherein the three or more processors are configured to execute a same process in parallel,
wherein the storage device includes a non-redundant memory mat having storage regions each corresponding to an address issued at a time of an access by a processor, an address selection part selecting a storage region in the memory mat on a basis of three or more addresses issued at a time of an access by the three or more processors, a data output part reading data from the storage region in the memory mat selected by the address selection part, and a failure recovery part correcting or masking a detected failure which occurs in the memory mat, the address selection part, or the data output part, and
wherein the address selection part comprises a plurality of address decoders and a majority logic circuit which selects the selected storage region by a result of majority vote of outputs of the plurality of address decoders.