US 9,811,420 B2
Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)
Debaleena Das, Los Gatos, CA (US); Bill Nale, Livermore, CA (US); Kuljit S Bains, Olympia, WA (US); and John B Halbert, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2015, as Appl. No. 14/670,413.
Prior Publication US 2016/0283318 A1, Sep. 29, 2016
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1084 (2013.01) [G06F 11/00 (2013.01); G06F 11/1008 (2013.01); G06F 11/1076 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for error correction in a memory subsystem, comprising:
performing internal error detection in a memory device to detect errors in read data in response to a read request from an associated memory controller, the internal error detection to be performed with internal check bits generated within the memory device;
selectively performing an internal error correction operation on the read data in response to detecting an error in the read data with the internal check bits;
generating check bits indicating an error vector for the read data to compare against the internal check bits for performing the internal error detection and correction; and
providing the check bits with the read data to the associated memory controller in response to the read request, the check bits for use by the associated memory controller in additional error correction external to the memory device.