US 9,811,417 B2
Semiconductor memory device
Masahiro Abe, Tokyo (JP)
Assigned to Toshiba Memory Corporation, Tokyo (JP)
Filed by Toshiba Memory Corporation, Minato-ku, Tokyo (JP)
Filed on Mar. 4, 2016, as Appl. No. 15/61,487.
Claims priority of provisional application 62/132,412, filed on Mar. 12, 2015.
Prior Publication US 2016/0266973 A1, Sep. 15, 2016
Int. Cl. G11C 29/00 (2006.01); G06F 11/10 (2006.01); H03M 13/27 (2006.01); H03M 13/35 (2006.01); G11C 29/04 (2006.01)
CPC G06F 11/1068 (2013.01) [H03M 13/2732 (2013.01); H03M 13/353 (2013.01); G11C 2029/0411 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
an encoder configured to generate an error correction code with respect to data;
a first processor configured to perform interleaving with respect to the data from the encoder after the generation of the error correction code;
a memory configured to store a process result from the first processor;
a detector configured to detect a credibility value indicative of credibility of the data read from the memory; and
a controller configured to determine whether or not the credibility value of the data read from a predetermined area of the memory is equal to or greater than a predetermined value based on a detection result from the detector, the controller configured to perform the interleaving with respect to the data read from the predetermined area if the credibility value is equal to or greater than the predetermined value and to withhold the interleaving with respect to the data read from the predetermined area if the credibility value is less than the predetermined value.