US 9,811,416 B2
Memory access method and apparatus for message-type memory module
Xiang Gao, Beijing (CN); Bing Li, Beijing (CN); Shuchang Shan, Beijing (CN); and Yu Hu, Beijing (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed on Jan. 29, 2016, as Appl. No. 15/10,326.
Application 15/010,326 is a continuation of application No. PCT/CN2014/083464, filed on Jul. 31, 2014.
Claims priority of application No. 2013 1 0330220 (CN), filed on Jul. 31, 2013.
Prior Publication US 2016/0147600 A1, May 26, 2016
Int. Cl. G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/108 (2013.01); G06F 11/1044 (2013.01); G11C 29/52 (2013.01)] 15 Claims
OG exemplary drawing
1. A memory access apparatus for a message-type memory module, wherein
the memory module comprises (M+2) dynamic random access memories (DRAMs), wherein M is equal to mth power of 2, m is a positive integer, data accessed in one read-write cycle and stored in each DRAM forms a single chip burst cluster (SCBC), and the SCBCs accessed in one read-write cycle of all the DRAMs form a memory row; and
the apparatus comprises:
a read-write module, configured to store a to-be-stored SCBC to a current memory row of a corresponding DRAM of the to-be-stored SCBC within a current read-write cycle, wherein an (M+2)th DRAM is not used to store the SCBC; and
a processing module, configured to: calculate an error detecting code for each SCBC in one memory row respectively, and calculate an error correcting code for all the SCBCs in one memory row; wherein
the read-write module is further configured to: store the calculated detecting codes in the (M+2)th DRAM of the memory row, and store, the calculated error correcting code of the memory row in a Zth DRAM, wherein Z is a positive integer, 1≤Z≤(M+1), and error correcting codes in consecutive (M+1) memory rows are stored in different DRAMs, wherein
the processing module is further configured to: determine whether a quantity of second SCBCs to-be-written X is less than or equal to M/2 when a write memory access request is received; and
if X is less than or equal to M/2, instruct the read-write module to read X first SCBCs stored in X DRAMs into which the second SCBCs are to be written, and X first error detecting codes of the X first SCBCs and a first error correcting code of current memory row; determine, according to the X first error detecting codes, whether there is a first SCBC with error; and when there is no first SCBC with error, calculate second error detecting codes for the X second SCBCs, calculate a second error correcting code according to the first error correcting code, the X first SCBCs, and the X second SCBCs, and instruct the read-write module to write the X second SCBCs, the second error correcting codes, and the second error detecting codes into corresponding DRAMs.