US 9,811,404 B2
Information processing system and method
Hiroki Sato, Yokohama (JP); and Eiju Shin, Kawasaki (JP)
Assigned to FUJITSU LIMITED, Kawasaki (JP)
Filed by FUJITSU LIMITED, Kawasaki-shi, Kanagawa (JP)
Filed on Jul. 22, 2015, as Appl. No. 14/805,952.
Claims priority of application No. 2014-153940 (JP), filed on Jul. 29, 2014.
Prior Publication US 2016/0034332 A1, Feb. 4, 2016
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/16 (2006.01)
CPC G06F 11/0724 (2013.01) [G06F 11/1629 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An information processing system comprising:
a first system that includes a first controller, a first external device, a first memory, and a first processor including a plurality of first processor cores configured to execute calculation with sharing the first memory; and
a second system that includes a second memory, and a second controller including a plurality of second processor cores configured to execute calculation, which is the same as calculation executed by the plurality of first processor cores, with shared access to the second memory based on a history of accesses to the first memory from the plurality of first processor cores,
wherein the first controller is configured to:
control the first external device to output first output data of a given calculation executed by the plurality of first processor cores in response to a match of a first result of the given calculation executed by the plurality of first processor cores with a second result of the given calculation executed by the plurality of second processor cores, the first output data being outputted from each of one or more first output processor cores of the plurality of first processor cores that have issued an output request for the given calculation,
determine whether the plurality of first processor cores include one or more first non-output processor cores that have not issued the output request for the given calculation,
control the one or more first output processor cores to be in a stopped state in response to obtaining the first output data, the one or more first output processor cores being controlled to restart in response to determining the first result and the second result match, and
control the one or more first non-output processor cores to calculate another given calculation in response to obtaining the first output data while the first output processors are in the stopped state.