US 9,811,403 B1
Method, apparatus and system for performing matching operations in a computing system
Sayantan Sur, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 22, 2016, as Appl. No. 15/189,103.
Int. Cl. G06F 3/00 (2006.01); G06F 9/44 (2006.01); G06F 9/46 (2006.01); G06F 13/00 (2006.01); G06F 9/54 (2006.01)
CPC G06F 9/546 (2013.01) [G06F 9/544 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of queues, wherein the plurality of queues includes a plurality of first entries to store receive information for a process and a plurality of replica wild card entries:
a master queue including a plurality of second entries to store wild card receive information, wherein redundant information stored in the plurality of second entries is to be included stored in the plurality of redundant replica wild card entries of the plurality of queues, each of the plurality of replica wild card entries to point to one of the second entries in the master queue: and
a control circuit to match an incoming receive operation within one of the plurality of queues, wherein the control circuit is to cause an atomic operation to occur between a matching replica wild card entry of a first queue of the plurality of queues and a corresponding second entry of the master queue, the atomic operation comprising a compare and swap operation to cause buffer information stored in the corresponding second entry of the master queue store in the matching replica wild card entry of the first queue, and wherein responsive to the compare and swap operation, data of the incoming receive operation is to be copied to a buffer of a first process, based at least in part on the buffer information.