US 9,811,397 B2
Direct application-level control of multiple asynchronous events
Giles R. Frazier, Austin, TX (US); and Michael Karl Gschwind, Chappaqua, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 2, 2015, as Appl. No. 14/930,354.
Application 14/930,354 is a continuation of application No. 14/876,950, filed on Oct. 7, 2015.
Prior Publication US 2017/0102964 A1, Apr. 13, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/00 (2006.01); G06F 3/00 (2006.01); G06F 9/44 (2006.01); G06F 9/46 (2006.01); G06F 9/54 (2006.01); G06F 9/48 (2006.01)
CPC G06F 9/542 (2013.01) [G06F 9/4818 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method, comprising:
reading, by operation of an application-level handler, the register containing a first plurality of bits storing status information for the plurality of facilities, wherein each of the plurality of facilities corresponds to a respective one or more bits in the first plurality of bits, wherein the register contains a second plurality of bits containing control information for the plurality of facilities, and wherein each of the plurality of facilities corresponds to a respective one or more bits in the second plurality of bits, wherein the status information indicates which facility of the plurality of facilities triggered an exception and the control information indicates whether additional exceptions can occur for the facility until an event that triggered the exception is handled, wherein a facility is a hardware unit running independently from a processor;
determining an order of priority for events associated with the plurality of facilities based on the status information and control information of the plurality of facilities;
processing the events in the order of priority such that an application can directly control the plurality of facilities simultaneously.