US 9,811,389 B2
Task assignment for processor cores based on a statistical power and frequency model
Tomer Rider, Naahyria (IL); Lev Faivishevsky, Kfar Saba (IL); Igor Ljubunicic, Yokneam Ilit (IL); Shahar Taite, Kfar Saba (IL); and Raphael Sack, Mitzpe Amuka (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2015, as Appl. No. 14/862,510.
Prior Publication US 2017/0083383 A1, Mar. 23, 2017
Int. Cl. G06F 9/46 (2006.01); G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 1/32 (2006.01)
CPC G06F 9/5094 (2013.01) [G06F 1/329 (2013.01); G06F 9/4893 (2013.01)] 24 Claims
OG exemplary drawing
1. An apparatus comprising:
a plurality of processor cores;
at least one memory coupled to the plurality of processor cores; and
task assigning circuitry to assign a first task, based the usage history, to one processor core for execution at maximum frequency with minimum power usage in comparison to other processor cores of the plurality, the usage history being based on monitored core temperature, frequency and power usage for a first set of tasks previously executed by the plurality of processor cores,
wherein the usage history is created by collecting data for a predetermined number of executions of an application, including monitoring execution times of tasks per quantum of time, monitoring processor utilization levels for each group of related tasks, monitoring memory utilization levels for each group of related tasks and overall memory utilization per quantum of time, and preprocessing gathered data, including calculating an estimate of dynamic power consumption based on measurements of core voltage, core frequency, and core capacitance; and computing an estimate of a probability density function based on a joint distribution of power, execution time, frequency, and processor and memory utilizations for each core per time period.