US 9,811,388 B2
VSync aligned CPU frequency governor sampling
Premal Shah, San Diego, CA (US); Rajulu Ponnada, Hyderabad (IN); and Omprakash Dhyade, San Diego, CA (US)
Assigned to QUALCOMM Innovation Center, Inc., San Diego, CA (US)
Filed by Qualcomm Innovation Center, Inc., San Diego, CA (US)
Filed on Mar. 16, 2016, as Appl. No. 15/72,248.
Claims priority of provisional application 62/161,656, filed on May 14, 2015.
Prior Publication US 2016/0335737 A1, Nov. 17, 2016
Int. Cl. G06F 9/54 (2006.01); G06F 9/50 (2006.01)
CPC G06F 9/5083 (2013.01) [G06F 9/54 (2013.01); G06T 2200/28 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A graphics processing system comprising:
a graphics processing circuit;
display hardware operating at a refresh rate f, the display hardware including:
a pulse generation circuit configured to generate pulses; and
a CPU circuit comprising a CPU frequency governor in electrical communication with the pulse generation circuit, the CPU frequency governor comprising:
a clock circuit;
a pulse input in electrical communication with the pulse generation circuit; and
a sampling window selection submodule configured to select a sampling window for the CPU frequency governor, the sampling window based on a signal from either the clock circuit or the pulse input, the sampling window based on the signal from the pulse input when a workload of the CPU is sporadic.