US 9,811,385 B2
Optimizing task management
Maarten Koning, Bloomfield (CA); and Stephen Li, Menlo Park, CA (US)
Assigned to WIND RIVER SYSTEMS, INC., Alameda, CA (US)
Filed by Maarten Koning, Bloomfield (CA); and Stephen Li, Menlo Park, CA (US)
Filed on Apr. 28, 2010, as Appl. No. 12/769,080.
Prior Publication US 2011/0271076 A1, Nov. 3, 2011
Int. Cl. G06F 9/50 (2006.01); G06F 1/00 (2006.01); G06F 9/46 (2006.01); G06F 9/30 (2006.01); G06F 9/48 (2006.01); G06F 1/32 (2006.01)
CPC G06F 9/5061 (2013.01) [G06F 9/30189 (2013.01); G06F 9/505 (2013.01); G06F 9/5094 (2013.01); G06F 1/3287 (2013.01); G06F 9/4881 (2013.01); Y02B 60/144 (2013.01)] 16 Claims
OG exemplary drawing
 
9. A method, comprising:
determining a number of user-operated tasks running on an electronic device, the electronic device comprising a processing array including a plurality of processing cores, the processing array being configurable for one of a single-core processing mode and a multi-core processing mode,
wherein the single-core processing mode comprises the processing component configured to execute an operating system in a first operating system mode using a first one of the processing cores, wherein the first operating system mode is optimized to perform a single task, and
wherein the multi-core processing mode comprises the processing array configured to execute the operating system in a second operating system mode using the first one of the processing cores and a second one of the processing cores, wherein the second operating system mode is optimized to perform multiple tasks; and
configuring the processing array to operate in the single-core processing mode or the multi-core processing mode based only on the number of user-operated tasks,
wherein the processing array operates in the single-core processing mode when the number of user-operated tasks is one and operates in the multi-core processing mode when the number of user-operated tasks is greater than one,
wherein the single-core processing mode enables only the single task to be executed and disables a multi-core processing architecture.