US 9,811,361 B2
Flexible allocation of I/O channels of a hardware component
Stefan Merten, Bielefeld (DE); Marc Schlenger, Paderborn (DE); Holger Ross, Muenster-Hiltrup (DE); and Frank Mertens, Bad Lippspringe (DE)
Assigned to dSPACE digital signal processing and control engineering GmbH, Paderborn (DE)
Filed by dSPACE digital signal processing and control engineering GmbH, Paderborn (DE)
Filed on Oct. 16, 2013, as Appl. No. 14/55,497.
Claims priority of application No. 10 2013 104 320 (DE), filed on Apr. 29, 2013.
Prior Publication US 2014/0324408 A1, Oct. 30, 2014
Int. Cl. G06F 9/44 (2006.01); G06F 13/10 (2006.01); G06F 13/12 (2006.01); G06F 9/455 (2006.01); G06F 17/50 (2006.01); G06F 15/78 (2006.01)
CPC G06F 9/455 (2013.01) [G06F 8/35 (2013.01); G06F 15/7871 (2013.01); G06F 17/5027 (2013.01); G06F 17/5054 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA (Field Programmable Gate Array), and a plurality of I/O (Input/Output) channels, the hardware component being connectable to a computer system, the I/O channels being connectable to the FPGA, and the FPGA being connectable to the processor via a communications interface, the method comprising:
selecting a first subset of the I/O channels for operation by the FPGA;
generating a first application program to be executed by the FPGA;
selecting a second subset of the I/O channels for operation by the processor based on the selected first subset of the I/O channels;
generating a second application program to be executed by the processor;
generating an application model for the hardware component,
embedding the first application program in the second application program,
storing the second application program with the embedded first application program in a memory assigned to the processor for execution by the processor, and
executing the first application program and the second application program,
wherein the step of generating the first application program comprises model-based automatic generation of code based on the application model for the hardware component,
wherein the step of generating a first application program comprises the generation of code for connecting the second subset of the I/O channels to the communications interface,
wherein the step of generating code for connecting the second subset of the I/O channels to the communications interface comprises the automatic generation of code for connecting I/O channels that are part of the second subset of I/O channels, and
based on the executed first application program and second application program, connecting the hardware component of the computer system, wherein the hardware component includes the I/O channels, the FPGA, and the processor, with the I/O channels connecting to the FPGA, and the FPGA connecting to the processor, via the communication interface.