US 9,811,355 B2
Method and apparatus for selecting an interconnect frequency in a computing system
Nir Rosenzweig, Givat Ella (IL); Efraim Rotem, Haifa (IL); Doron Rajwan, Rishon Le-Zion (IL); Nadav Shulman, Tel Mond (IL); and Eliezer Weissmann, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 23, 2014, as Appl. No. 14/338,692.
Prior Publication US 2016/0026479 A1, Jan. 28, 2016
Int. Cl. G06F 1/32 (2006.01); G06F 9/445 (2006.01); G06F 12/0844 (2016.01); G06F 13/42 (2006.01)
CPC G06F 9/44505 (2013.01) [G06F 12/0844 (2013.01); G06F 13/4234 (2013.01); G06F 1/324 (2013.01); G06F 2212/604 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01)] 20 Claims
OG exemplary drawing
1. A processor comprising:
a semiconductor die including:
at least one core;
a cache memory;
an interconnect that couples the at least one core and the cache memory, the interconnect to operate at an interconnect frequency; and
a power management unit (PMU) including first logic to determine whether to adjust the interconnect frequency responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor, the Bayesian prediction value to indicate whether the workload is scalable with respect to the interconnect frequency, wherein the Bayesian prediction value is determined based on one or more activity measures associated with the processor.