US 9,811,344 B2
Core ID designation system for dynamically designated bootstrap processor
G. Glenn Henry, Austin, TX (US); and Stephan Gaskins, Austin, TX (US)
Assigned to VIA TECHNOLOGIES, INC., New Taipei (TW)
Filed by VIA TECHNOLOGIES, INC., New Taipei (TW)
Filed on Nov. 21, 2016, as Appl. No. 15/357,145.
Application 15/357,145 is a continuation of application No. 14/281,729, filed on May 19, 2014, granted, now 9,535,488.
Claims priority of provisional application 61/871,206, filed on Aug. 28, 2013.
Claims priority of provisional application 61/916,338, filed on Dec. 16, 2013.
Prior Publication US 2017/0068546 A1, Mar. 9, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/00 (2006.01); G06F 9/38 (2006.01); G06F 1/32 (2006.01); G06F 12/084 (2016.01); G06F 13/24 (2006.01); G06F 9/44 (2006.01); G06F 13/364 (2006.01); G06F 12/0808 (2016.01); G06F 9/30 (2006.01); G06F 12/0875 (2016.01); G06F 1/04 (2006.01); G06F 1/12 (2006.01); G06F 13/42 (2006.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01); H04L 9/08 (2006.01); H01L 21/66 (2006.01)
CPC G06F 9/3885 (2013.01) [G06F 1/04 (2013.01); G06F 1/12 (2013.01); G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3237 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 9/30032 (2013.01); G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/30087 (2013.01); G06F 9/30105 (2013.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01); G06F 9/3861 (2013.01); G06F 9/4403 (2013.01); G06F 9/4405 (2013.01); G06F 9/4411 (2013.01); G06F 9/4418 (2013.01); G06F 12/084 (2013.01); G06F 12/0808 (2013.01); G06F 12/0875 (2013.01); G06F 13/24 (2013.01); G06F 13/364 (2013.01); G06F 13/42 (2013.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6028 (2013.01); G06F 2212/62 (2013.01); H01L 22/34 (2013.01); H04L 9/0877 (2013.01); H04L 9/0897 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1221 (2013.01); Y02B 60/1282 (2013.01); Y02B 60/1285 (2013.01); Y02B 60/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microprocessor, comprising:
an indicator; and
a plurality of processing cores, each configured to generate a default core ID number for itself, wherein each default core ID is unique;
wherein each of the plurality of processing cores is configured to sample the indicator;
wherein when the indicator indicates a first predetermined value, the default core ID generated by a default one of the processing cores designates the default processing core to be a bootstrap processor; and
wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are each configured to generate alternate core IDs that are different from the default core IDs, wherein one of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor.