US 9,811,341 B2
Managed instruction cache prefetching
Kyriakos A. Stavrou, Barcelona (ES); Enric Gibert Codina, Barcelona (ES); Josep M. Codina, Hospitalet de Llobregat (ES); Crispin Gomez Requena, Valencia (ES); Antonio Gonzalez, Barcelona (ES); Mirem Hyuseinova, Barcelona (ES); Christos E. Kotselidis, Linz (AT); Fernando Latorre, Barcelona (ES); Pedro Lopez, Molins de Rei (ES); Marc Lupon, Barcelona (ES); Carlos Madriles Gimeno, Barcelona (ES); Grigorios Magklis, Barcelona (ES); Pedro Marcuello, Barcelona (ES); Alejandro Martinez Vicente, Barcelona (ES); Raul Martinez, Barcelona (ES); Daniel Ortega, Barcelona (ES); Demos Pavlou, Barcelona (ES); Georgios Tournavitis, Barcelona (ES); and Polychronis Xekalakis, Barcelona (ES)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 13/995,649
Filed by Kyriakos A. Stavrou, Barcelona (ES); Enric Gibert Codina, Barcelona (ES); Josep M. Codina, Hospitalet de Llobregat (ES); Crispin Gomez Requena, Valencia (ES); Antonio Gonzalez, Barcelona (ES); Mirem Hyuseinova, Barcelona (ES); Christos E. Kotselidis, Linz (AT); Fernando Latorre, Barcelona (ES); Pedro Lopez, Molins de Rei (ES); Marc Lupon, Barcelona (ES); Carlos Madriles Gimeno, Barcelona (ES); Grigorios Magklis, Barcelona (ES); Pedro Marcuello, Barcelona (ES); Alejandro Martinez Vicente, Barcelona (ES); Raul Martinez, Barcelona (ES); Daniel Ortega, Barcelona (ES); Demos Pavlou, Barcelona (ES); Georgios Tournavitis, Barcelona (ES); and Polychronis Xekalakis, Barcelona (ES)
PCT Filed Dec. 29, 2011, PCT No. PCT/US2011/067964
§ 371(c)(1), (2), (4) Date Jun. 19, 2013,
PCT Pub. No. WO2013/101121, PCT Pub. Date Jul. 4, 2013.
Prior Publication US 2014/0019721 A1, Jan. 16, 2014
Int. Cl. G06F 9/38 (2006.01); G06F 9/30 (2006.01); G06F 12/0862 (2016.01)
CPC G06F 9/3804 (2013.01) [G06F 9/3017 (2013.01); G06F 9/30047 (2013.01); G06F 9/3802 (2013.01); G06F 9/3806 (2013.01); G06F 9/3848 (2013.01); G06F 12/0862 (2013.01); G06F 2212/452 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A method to manage instruction cache prefetching from an instruction cache comprising:
storing information about instruction cache misses, wherein the information includes an instruction cache line address, branch target characteristics including a type of branch indicator, the confidence of the prediction, and a branch address;
identifying common instruction cache misses; predicting the outcome of a branch and providing a confidence of the prediction;
for an indirect branch, inserting, regardless of the confidence, a prefetch instruction from a prefetch engine to the instruction cache; and
for a direct branch, inserting the prefetch instruction from the prefetch engine to the instruction cache is based upon whether the taken branch had a strong prediction or a weak prediction and the prefetch instruction is executed or not executed dependent upon the confidence of the prediction.