US 9,811,339 B1
Testing hybrid instruction architecture
Ali Y. Duale, Poughkeepsie, NY (US); Shailesh R. Gami, Poughkeepsie, NY (US); and Dennis W. Wittig, Poughkeepsie, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Mar. 8, 2017, as Appl. No. 15/452,905.
Application 15/452,905 is a continuation of application No. 15/273,850, filed on Sep. 23, 2016.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/22 (2006.01); G06F 9/30 (2006.01); G06F 11/36 (2006.01)
CPC G06F 9/30145 (2013.01) [G06F 9/30072 (2013.01); G06F 9/30181 (2013.01); G06F 11/3688 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for testing a hybrid architecture instruction set, the method comprising:
defining a first instruction definition table for a first base architecture;
defining a second instruction definition table for a second base architecture, wherein the first base architecture is different than the second base architecture;
defining a delta table;
generating a hybrid architecture table based on the delta table; and
executing a test based on the hybrid architecture table.