US 9,811,338 B2
Flag non-modification extension for ISA instructions using prefixes
Jonathan D. Combs, Austin, TX (US); Jason W. Brandt, Austin, TX (US); and Robert Valentine, Kiryat Tivon (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 13/976,261
Filed by Jonathan D. Combs, Austin, TX (US); Jason W. Brandt, Austin, TX (US); and Robert Valentine, Kiryat Tivon (IL)
PCT Filed Nov. 4, 2011, PCT No. PCT/US2011/060645
§ 371(c)(1), (2), (4) Date Jun. 26, 2013,
PCT Pub. No. WO2013/074074, PCT Pub. Date May 23, 2013.
Prior Publication US 2013/0297915 A1, Nov. 7, 2013
Int. Cl. G06F 9/30 (2006.01)
CPC G06F 9/30145 (2013.01) [G06F 9/30094 (2013.01); G06F 9/30185 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
in response to decoding an instruction having a prefix and an opcode received at a processor, wherein the prefix includes a vector length bit when the opcode includes a vector instruction that is supported by the processor,
executing, by an execution unit of the processor, the instruction based on the opcode; and
preventing the execution unit from modifying a flag register of the processor based on the vector length bit of the prefix of the instruction.