US 9,811,334 B2
Block operation based acceleration
Ben Ashbaugh, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 6, 2013, as Appl. No. 14/99,215.
Prior Publication US 2015/0161758 A1, Jun. 11, 2015
Int. Cl. G06T 1/60 (2006.01); G06F 13/00 (2006.01); G06F 9/30 (2006.01); G06F 12/00 (2006.01); G06T 1/20 (2006.01)
CPC G06F 9/30 (2013.01) [G06F 12/00 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a display;
a shared local memory;
a data register; and
a processor configured to execute:
a scalar module to define a plurality of execution elements, wherein two or more of the execution elements are to be grouped into an element block; and
a block module to be invoked by the scalar module and implement a block operation on a data block, wherein the block operation is to include a data transfer event between system memory and the data register excluding the shared local memory to be performed by the two or more execution elements of the element block simultaneously by an access to one memory address in the system memory for the entire data block that does not explicitly define a width of the data block, wherein the width of the data block is to be implicitly defined based on the number of execution elements in the element block, and wherein the display is to render data based on the block operation.