US 9,811,318 B2
Montgomery multiplication method for performing final modular reduction without comparison operation and montgomery multiplier
Jonghoon Shin, Hwaseong-si (KR); Sun-Soo Shin, Seoul (KR); Kyoungmoon Ahn, Seoul (KR); and Yong Ki Lee, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do (KR)
Filed on Mar. 30, 2015, as Appl. No. 14/672,656.
Claims priority of application No. 10-2014-0037898 (KR), filed on Mar. 31, 2014.
Prior Publication US 2015/0277855 A1, Oct. 1, 2015
Int. Cl. G06F 7/72 (2006.01); G06F 7/533 (2006.01)
CPC G06F 7/728 (2013.01) [G06F 7/5338 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A Montgomery multiplier apparatus, comprising:
a partial product computing unit configured to multiply a multiplicand and a multiplier;
a modulus reduction computing unit configured to multiply a modulus and a quotient with a quotient sign, wherein the quotient is zero during a first cycle;
an accumulation unit configured to accumulate in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle;
a quotient computing unit configured to receive an accumulation value of the accumulation unit during a current cycle and to calculate a quotient to be used during a next cycle; and
a quotient sign determination unit configured to determine the quotient sign to be used during the next cycle from the multiplicand, the multiplier and the quotient.