US 9,811,273 B1
System and method for reliable high-speed data transfer in multiple data rate nonvolatile memory
Sandeep Brahmadathan, Bangalore (IN)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US)
Filed on Dec. 23, 2014, as Appl. No. 14/580,833.
Int. Cl. G11C 29/00 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 29/52 (2013.01); G06F 2206/1014 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for reliable high speed data transfer in multiple data rate nonvolatile memory, the method comprising:
establishing a memory controller and a nonvolatile memory having a communication link therebetween;
establishing a range of delay values representing relative delay between a plurality of data signals and a data strobe signal for data transmission from the memory controller to the nonvolatile memory through the communication link;
selectively establishing a training portion in the nonvolatile memory defined based on a smallest erasable unit of the nonvolatile memory;
providing at least one known data pattern;
executing the memory controller to:
sequentially write the known data pattern to different segments of the training portion of the nonvolatile memory, the known data pattern being written repetitively in the segments of the training portion and relative to the data strobe signal at different delay values within the established range for each written segment;
sequentially read each of the segments to compare the data pattern read with the known data pattern and thereby identify each correctly written segment, a first of the correctly written segments defining a leading edge of alignment between data and data strobe signals, a last of the correctly written segments defining a trailing edge of alignment between data and data strobe signals; and
establish an optimal delay value as a mean delay value between the delay values of the leading and trailing edge alignment, subsequent write operations to the nonvolatile memory being executed based on the optimal delay value.