US 9,811,270 B2
Semiconductor storage device and controller
Hiroshi Maejima, Tokyo (JP)
Assigned to Toshiba Memory Corporation, Tokyo (JP)
Filed by TOSHIBA MEMORY CORPORATION, Tokyo (JP)
Filed on Oct. 28, 2016, as Appl. No. 15/337,852.
Application 15/337,852 is a continuation of application No. 14/833,719, filed on Aug. 24, 2015, granted, now 9,514,825.
Application 14/833,719 is a continuation of application No. 13/779,427, filed on Feb. 27, 2013, granted, now 9,153,325, issued on Oct. 6, 2015.
Claims priority of application No. 2012-128727 (JP), filed on Jun. 6, 2012.
Prior Publication US 2017/0046078 A1, Feb. 16, 2017
Int. Cl. G11C 16/10 (2006.01); G06F 3/06 (2006.01); G11C 16/16 (2006.01); G06F 12/02 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01)
CPC G06F 3/0614 (2013.01) [G06F 3/0631 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0665 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G11C 11/5635 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/3418 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/152 (2013.01); G06F 2212/214 (2013.01); G06F 2212/7202 (2013.01); G11C 2213/71 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A storage device comprising:
a first memory string including a first memory cell, a second memory cell, and a first selection transistor;
a second memory string including a third memory cell, a fourth memory cell, and a second selection transistor;
a third memory string including a fifth memory cell, a sixth memory cell, and a third selection transistor;
a bit line coupled to the first, second, and third memory strings;
a first word line coupled to gates of the first memory cell, the third memory cell, and the fifth memory cell; and
a second word line coupled to gates of the second memory cell, the fourth memory cell, and the sixth memory cell,
wherein a first page address is allocated to a page associated with the first memory cell, a second page address is allocated to a page associated with the third memory cell, a third page address is allocated to a page associated with the fifth memory cell, a fourth page address is allocated to a page associated with the second memory cell, a fifth page address is allocated to a page associated with the fourth memory cell, and a sixth page address is allocated to a page associated with the sixth memory cell.