US 9,811,269 B1
Achieving consistent read times in multi-level non-volatile memory
Anand S. Ramalingam, Beaverton, OR (US); and Pranav Kalavade, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 30, 2016, as Appl. No. 15/395,062.
Int. Cl. G11C 7/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0652 (2013.01); G06F 3/0656 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/0253 (2013.01); G06F 12/0292 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/2022 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A system comprising:
a device controller apparatus including a transfer buffer, and
a non-volatile memory (NVM) communicatively coupled to the device controller apparatus, the NVM including a set of multi-level NVM cells and a chip controller apparatus that includes a substrate and logic, implemented in fixed-functionality hardware and coupled to the substrate, the logic to:
read a lower page from the set of multi-level NVM cells,
read one or more intermediate pages from the set of multi-level NVM cells, and
read a last page from the set of multi-level NVM cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is to be substantially similar to an intermediate read time associated with the one or more intermediate pages.