US 9,811,266 B1
Data buffer for multiple DIMM topology
Yang Sun, Hangzhou (CN)
Assigned to CISCO TECHNOLOGY, INC., San Jose, CA (US)
Filed by CISCO TECHNOLOGY, INC., San Jose, CA (US)
Filed on Sep. 22, 2016, as Appl. No. 15/273,274.
Int. Cl. G11C 16/04 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0683 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A system comprising:
a memory controller circuit element, and
a printed circuit board (PCB), the PCB comprising:
a memory module element; and
a data buffer circuit element, the data buffer circuit element electrically connected to the memory controller circuit element and configured to receive instructions and data from the memory controller circuit element, the data buffer circuit element electrically connected to the memory module circuit element, the data buffer circuit element configured to transmit instructions and data originated from the memory controller circuit element to the memory module circuit element and transmit data back to the memory controller circuit element.