US 9,811,263 B1
Memory controller architecture with improved memory scheduling efficiency
Chee Hak Teh, Bayan Lepas (MY)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Altera Corporation, San Jose, CA (US)
Filed on Jun. 30, 2014, as Appl. No. 14/319,103.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for operating memory controller circuitry that communicates with external memory, the method comprising:
receiving a memory access request at the memory controller circuitry, wherein the memory controller circuitry includes a plurality of color pipelines that are operated in parallel to process memory access requests for different portions of the external memory;
decoding the memory access request to identify a target portion of the external memory that is to be accessed; and
determining whether the target portion of the external memory has already been assigned to one of the plurality of color pipelines.