US 9,811,150 B2
System and method for controlling idle state exits to manage DI/DT issues
Malcolm S. Allen-Ware, Tucson, AZ (US); Alan James Drake, Austin, TX (US); Michael Stephen Floyd, Cedar Park, TX (US); Charles Robert Lefurgy, Austin, TX (US); Karthick Rajamani, Austin, TX (US); and Tobias Webel, Schwaebisch Gmuend (DE)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 10, 2015, as Appl. No. 14/937,290.
Claims priority of application No. 1420013.3 (GB), filed on Nov. 11, 2014.
Prior Publication US 2016/0132096 A1, May 12, 2016
Int. Cl. G06F 1/32 (2006.01); G06F 1/26 (2006.01); G06F 9/44 (2006.01)
CPC G06F 1/3287 (2013.01) [G06F 1/26 (2013.01); G06F 9/4418 (2013.01); Y02B 60/1282 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises:
determining, by a chip power management unit of the processor, for each processor core if the processor core is currently in an idle state, wherein the chip power management unit is external to the core units;
maintaining, by the chip power management unit based on the determining, an idle state count indicating a number of processor cores currently in the idle state;
entering, by the chip power management unit, an armed mode when the idle state count indicates exceeds an idle state count threshold, wherein the armed mode places the chip power management unit in a state where the chip power management unit is ready to delay command execution by one or more of the core units after they exit the idle state;
detecting, by the chip power management unit, idle state exits indicated by the core units;
maintaining, by the chip power management unit based on the detecting, an idle state exit count indicating a number of processor cores that have exited the idle state;
delaying, by the chip power management unit, a command execution of at least one of the core units indicating an idle state exit when the idle state exit count exceeds an idle state exit count threshold when the chip power management unit is in the armed mode; and
leaving, by the chip power management unit, the armed mode when the idle state count is less than the idle state count threshold.