US 9,811,148 B2
Static power reduction in caches using deterministic naps
Oluleye Olorode, Pflugerville, TX (US); and Mehrdad Nourani, Plano, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 14, 2017, as Appl. No. 15/431,922.
Application 15/431,922 is a division of application No. 14/694,285, filed on Apr. 23, 2015, abandoned.
Claims priority of provisional application 61/983,216, filed on Apr. 23, 2014.
Prior Publication US 2017/0153691 A1, Jun. 1, 2017
Int. Cl. G06F 1/32 (2006.01); G06F 12/08 (2016.01); G06F 12/0846 (2016.01); G06F 12/0811 (2016.01)
CPC G06F 1/3275 (2013.01) [G06F 12/0811 (2013.01); G06F 12/0848 (2013.01); G06F 2212/282 (2013.01); G06F 2212/283 (2013.01)] 2 Claims
OG exemplary drawing
 
1. A cache memory system responsive to access requests, each access request having a corresponding request memory address, said cache memory system operable on an operation pipeline having plural stages, comprising:
a cache memory operable to store data in a plurality of locations defined by a plurality of addresses and divided into a plurality of cache ways, said cache memory including a data memory array storing data and a tag memory array storing a predetermined number of most significant address bits of memory addresses of data stored in said data memory array in corresponding cache lines, said data memory array having plural cache lines grouped into plural individually powered groups, each individually powered group of cache lines receiving one of a first voltage enabling data access and a second voltage lower than said first voltage enabling data retention but not data access and said tag memory array receiving said first voltage;
a set decoder receiving said request memory address of an access request, said set decoder operable to
during a first pipeline stage during which said request memory address is received, determine from a set portion of said request memory address one of said individually powered groups of cache lines to which said access request is directed if said cache memory stores said corresponding data,
during a second pipeline stage immediately following said first pipeline stage, supply said first voltage to said determined individually powered group of cache lines and supply said second voltage to all other individually powered group of cache lines;
a tag comparator receiving said request memory of said access request and connected to said tag memory array, said tag comparator operable to
during said first pipeline stage, recall tag addresses from said tag memory array of said set of cache lines determined by said set decoder,
during said second pipeline stage, comparing a tag portion of said request address with each recalled tag address, determining a cache hit if any recalled tag address matches said tag portion of said request address, and
during a third pipeline stage immediately following said second pipeline stage, upon a cache hit supply said first voltage to a way of said determined individually powered group of cache lines triggering said cache hit and supply said second voltage to all other ways of said determined individually powered group of cache lines triggering said cache hit.